/* $Id: fse_em_verify.sv,v 1.1.1.1 2013-10-21:14:55:02 jzhao Exp $ */
/*
 * Authors:	jzhao@localhost.localdomain
 * Create Time:	2013-10-21:14:55:02
 * Description:	
 * 
 */

// `include "fse_em_verify.svh"
`define FSE_TOP   fxu_mul_top


module Mfxu_mul_verify(/*autoarg*/
   // Outputs
   vo_result_sn,
   // Inputs
   vi_op_sn
   );
		
   input logic  [31:0]        vi_op_sn;
   // input [31:0] 	vi_bypass_sn;
   output logic [31:0] 		  vo_result_sn;
   // clk ;
   // bit 					rst_n; 
   
 /*--------------sn transfer----------------------*/
   parameter STAGE = 4;
   
   logic [STAGE:0][31:0] 	  sn_ps_r;
   
   assign sn_ps_r[0] = vi_op_sn;
   
   generate
	  genvar 			i;
	  for(i=0;i<STAGE;i++)
		begin
		   always_ff@(posedge `FSE_TOP.clk)
			 begin
				if(`FSE_TOP.pipeline_stage_en[i])
				  sn_ps_r[i+1] <= sn_ps_r[i];
			 end
		end
   endgenerate
   
   assign vo_result_sn = sn_ps_r[STAGE];

endmodule // Mfxu_mul_verify

